DHRUV64: India’s First 1.0 GHz 64-bit Dual-Core RISC-V Microprocessor

DHRUV64 is India’s first 1.0 GHz, 64-bit dual-core RISC-V microprocessor — and the third chip fabricated under the Digital India RISC-V (DIR-V) Programme of the Ministry of Electronics and Information Technology. Released in December 2025, it represents the most capable indigenous processor produced by the Indian semiconductor design ecosystem to date.

What DHRUV64 is

DHRUV64 (sometimes referred to as VEGA AS2161 in C-DAC’s internal designation) is a System-on-Chip (SoC) built around two 64-bit RISC-V cores running at 1.0 GHz. It carries the architectural ingredients expected of a modern application-class processor:

• Two RV64GC cores with multiple cache levels (L1 instruction, L1 data, shared L2)
• Memory Management Unit (MMU) supporting page-based virtual memory and full Linux operating systems
• Floating-point unit (FPU) and integer multiply-divide
• AXI bus interconnect for peripheral attachment
• Interrupt controller (PLIC) and CLINT timer
• Standard peripherals — UART, SPI, I2C, GPIO, Ethernet MAC, USB controller

The chip was fabricated on a 28-nanometre process node at a foundry in Taiwan. While 28 nm is well behind the 3-5 nm bleeding edge of consumer mobile and PC processors, it is the sweet spot for industrial, embedded, automotive, and infrastructure compute — exactly the segments the DIR-V Programme is targeting.

Where it sits in the DIR-V family

The DIR-V Programme has now produced three chips in sequence:

1. THEJAS32 — a 32-bit single-core RISC-V processor, fabricated at Silterra in Malaysia. Aimed at IoT and embedded controllers.

2. THEJAS64 — a 64-bit single-core RISC-V processor, fabricated domestically at Semiconductor Laboratory (SCL), Mohali — the first indigenous fab. A step up in instruction-set width and intended for slightly heavier embedded workloads.

3. DHRUV64 — the dual-core, 1.0 GHz, application-class processor. Capable of running mainstream Linux distributions, suitable for industrial PCs, automotive infotainment, military embedded systems, scientific instruments, and educational use.

This trajectory deliberately follows the RISC-V community’s path internationally — from microcontroller-class cores (SiFive E-series) to application-class cores (U-series equivalents). DHRUV64 is C-DAC’s first application-class processor.

Who designed it

DHRUV64 was designed by the Centre for Development of Advanced Computing (C-DAC) under the Microprocessor Development Programme (MDP) sponsored by the Ministry of Electronics and IT. C-DAC’s Bengaluru centre led the architectural and verification work. C-DAC’s Trivandrum centre contributed to the SoC integration and physical design.

The processor IP is fully Indian — designed, verified, and tested by C-DAC engineers — with the foundry step (mask making and wafer fabrication) outsourced to Taiwan. The “indigenous” designation is therefore at the design and verification layer, not yet at the manufacturing layer. The aspiration is that subsequent versions will be fabricated at India Semiconductor Mission (ISM) fabs as they come online — Micron’s Sanand facility for assembly and test, the Tata-PSMC fab planned for Dholera, and the SCL Mohali expansion.

Why RISC-V matters

RISC-V is an open-standard instruction set architecture (ISA) developed at UC Berkeley and now governed by the RISC-V International consortium. Unlike Intel’s x86 or Arm’s ISAs, the RISC-V specification is royalty-free. Any organisation can design a processor implementing the RISC-V ISA without paying licence fees to a central owner.

For India, this matters in three ways:

Strategic autonomy

Indian defence, telecommunications, and critical-infrastructure systems have relied on imported processor IP (Arm cores, x86 chips). Geopolitical disruptions in semiconductor supply — most visibly during the 2020-22 chip shortage — exposed the fragility of this dependence. RISC-V allows India to build the entire processor design domestically without licensing dependence on a foreign ISA owner.

Educational and research access

RISC-V’s openness makes it the ideal teaching ISA for the new wave of Indian semiconductor engineering programmes. C-DAC has published the DHRUV64 design as a reference for educational and startup use.

Startup ecosystem

A number of Indian semiconductor startups — Mindgrove Technologies, InCore Semiconductors, Calligo Technologies — have built RISC-V-based products with C-DAC’s reference designs and Software Development Kits as starting points. DHRUV64 is intended to serve as a higher-end reference for startups building application-class systems.

Specifications summary

Target applications

DHRUV64’s positioning is mid-range industrial and infrastructure compute, not consumer or mobile. The expected deployments include:

• Industrial automation controllers — programmable logic controllers and SCADA gateways
• Embedded Linux systems in defence and aerospace platforms
• Scientific instrumentation — particle detectors, radio astronomy, oceanographic sensors
• Educational platforms — engineering colleges and research institutes
• Telecom infrastructure — 5G base station control planes (not the high-speed signal processing, which remains domain of specialised DSPs)

It is not aimed at the smartphone, PC, or data centre market, where Arm and x86 cores at 3-5 nm process nodes hold decisive performance advantages.

What comes next

C-DAC and the Ministry of Electronics and IT have signalled three follow-on directions:

• DHRUV-class multi-core variants with 4-8 cores for higher-throughput workloads
• Advanced process nodes — once domestic fabs reach 14 nm and below
• AI accelerator integration — pairing RISC-V cores with neural-network coprocessors for embedded AI inference

These plans align with the broader India Semiconductor Mission targets — design-led manufacturing as the first phase, evolving towards full end-to-end fabrication as fab capacity comes online.

FAQs

What is DHRUV64?

India’s first indigenously designed 1.0 GHz, 64-bit dual-core RISC-V microprocessor. Developed by C-DAC under the DIR-V Programme of the Ministry of Electronics and IT.

Is DHRUV64 the first chip under the DIR-V Programme?

No. It is the third. The first was THEJAS32 (32-bit single core, fabricated in Malaysia). The second was THEJAS64 (64-bit single core, fabricated at SCL Mohali in India). DHRUV64 is the first dual-core 64-bit chip in the programme.

Where was DHRUV64 fabricated?

At a foundry in Taiwan on a 28-nanometre process node. The design and verification work was entirely Indian (C-DAC); only the mask-making and wafer fabrication step was outsourced.

What does RISC-V mean?

An open-standard instruction set architecture (ISA) developed at UC Berkeley and governed by the RISC-V International consortium. Royalty-free, allowing anyone to design a compatible processor.

Can DHRUV64 run Linux?

Yes. With a Memory Management Unit, multi-level cache, and 64-bit virtual addressing, DHRUV64 supports mainstream Linux distributions (Ubuntu RISC-V port, Debian RISC-V, others) and full-featured operating environments.

What are the target applications?

Industrial automation, defence and aerospace embedded systems, scientific instrumentation, educational platforms, and telecom infrastructure control planes. Not consumer mobile or PC.

Who designed DHRUV64?

The Centre for Development of Advanced Computing (C-DAC), with the Bengaluru centre leading architectural design and verification and the Trivandrum centre contributing SoC integration.

How does it compare to Arm or x86 chips?

At 28 nm and 1.0 GHz, DHRUV64 is well behind the 3-5 nm Arm and x86 cores in consumer products. It is competitive in the industrial-embedded category, where 28 nm process nodes and 1 GHz clock speeds are still mainstream. The strategic value lies in indigenous design ownership, not raw consumer-grade performance.