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Government notifies Semicon 2.0 Scheme

Why in News?

The Ministry of Electronics and Information Technology (MeitY) has notified Semicon India 2.0, with a multi-year outlay of ₹1,27,500 crore. 

Announced in the Union Budget 2026-27, the scheme expands government support from individual fabrication and packaging projects to the entire semiconductor value chain. 

UPSC Relevance: GS-3 Economy: Manufacturing, Industrial Policy; Science and Technology: Frontier Technology

Prelims: India Semiconductor Mission, ISM 2.0  
Mains: Semiconductors: Role in economic growth & challenges associated

India Semiconductor Mission 2.0:  

  • Objective: To develop the complete semiconductor value chain: from indigenous chip design and specialised materials to fabrication, packaging, research and workforce development.
  • Outlay: ₹1,27,500 crore
  • Nodal Agency: India Semiconductor Mission (ISM). It will invite applications, undertake technical and financial appraisal, recommend applicants and oversee implementation.
  • MeitY will make budgetary provisions for fiscal support, with disbursements undertaken by the nodal agency in accordance with approved conditions. 
  • Projects supported under Semicon 2.0 will generally have a duration of up to six years, while the scheme will initially remain open for applications for three years.

A mid-term assessment will be conducted after three years of implementation (or as required) to evaluate the scheme’s impact and consider modifications or continuation.

Six Pillars of India Semiconductor Mission 2.0:  

  • Pillar 1 Design: It follows a three-track approach:
    • Strategic technologies: C-DAC will invite bids for Indian development of IP, chips, SoCs and modules for compute, memory, radio frequency, power, networking and sensors. The resulting IP will be jointly owned by C-DAC and the selected company.
    • Commercial fabless companies: Start-ups and MSMEs can receive milestone-linked seed funding of up to ₹15 crore or 50% of project cost (whichever is lower), and access to EDA tools, multi-project wafer services and post-silicon validation. 
    • Deployment-linked incentive: Newly developed chips can receive reimbursement equal to 9% of net sales for five years, capped at ₹30 crore per application and ₹120 crore per company group.
  • Pillar 2 Machines and Materials: Semiconductor manufacturing ecosystem.
  • Pillar 3 Setting up more Fabs: Silicon Semiconductor Wafer Fabs; Compound Semiconductors/Photonics/Sensors (including MEMS) Fab/Discrete Semiconductors Fab; and Display Fabs.
  • Pillar 4 Strengthening the ATMP/OSAT industry: Semiconductor Assembly, Testing, Marking and Packaging (ATMP) / Outsourced Semiconductor Assembly and Test (OSAT) Facility.
  • Pillar 5 Research and Development: R&D for advanced semiconductor technologies.
  • Pillar 6 Talent Development:  Semicon 2.0 seeks to train one lakh additional semiconductor engineers. 

Incentive Structure: 

  • Equipment and materials: 30% capital support for equipment, wafers, photomasks, substrates, photoresists, chemicals, gases and testing facilities. Equipment manufacturers can additionally receive a production-linked incentive declining from 10% to 2% over five years.
  • Silicon wafer fabs: 40% of eligible capital expenditure.
  • Other fabs: Compound-semiconductor, photonics, sensor, discrete-semiconductor and display fabs can receive up to 35%.
  • Advanced packaging: 35% capital support, compared with 25% for conventional packaging.
  • R&D and talent development: Support of up to 75% of project cost, including State incentives.

From ISM 1.0 to ISM 2.0: 

  • Launched in 2021 with an outlay of ₹76,000 crore, ISM 1.0 concentrated on attracting fabs, display units, packaging facilities and chip-design companies.
  • Its progress includes:
  • 12 manufacturing projects involving investment exceeding ₹1.64 lakh crore:
    • one silicon fab, one silicon-carbide fab, an integrated gallium-nitride micro-LED display fab and nine packaging units
    • commercial production by Micron, Kaynes and CG Semi
    • financial support for 24 chip-design projects
    • access to advanced design tools for 105 start-ups and MSMEs; and
    • semiconductor-design training for around 70,000 students across 332 universities. 

ISM 2.0 marks a shift from attracting isolated factories to creating an integrated ecosystem of design → equipment and materials → fabrication → packaging and testing → end-use manufacturing.

Significance of India Semiconductor Mission 2.0:  

  • Complete ecosystem: It links chip design, equipment, materials, fabrication, packaging, R&D and skilling, moving beyond support for isolated factories.
  • Technological sovereignty: Full-stack Indian intellectual property can reduce dependence on foreign chip architectures and enable customised chips for telecom, automobiles, space and defence.
  • Supply-chain resilience: Domestic capacity can reduce exposure to geopolitical conflicts, export controls and semiconductor shortages.
  • National security: Trusted indigenous chips are essential for defence systems, satellites, power grids, telecommunications and other critical infrastructure.
  • Industrial deepening: Demand for precision machinery, speciality chemicals, gases and advanced materials can generate spillovers across aerospace, medical equipment and high-end capital goods.
  • Higher domestic value addition: India can progress from electronics assembly to higher-value chip design, fabrication and advanced packaging.
  • Commercialisation and employment: Support for risk capital, prototyping and training can bridge the “lab-to-fab” gap while creating specialised jobs in design and manufacturing.
  • Strategic-sector growth: Domestic chips can accelerate EVs, AI, renewable energy, 6G, industrial automation, drones and medical devices.
  • Global positioning: India can leverage its large market and engineering base to emerge as a trusted partner in diversified global semiconductor supply chains.

Semicon 2.0 aims to strengthen India’s economic growth and national security by improving semiconductor supply-chain resilience and establishing technological leadership in critical sectors. Thus, it represents a shift from subsidising isolated chip factories to building an integrated semiconductor ecosystem. 

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Written by

Pooja Bhatt Ma'am

Editor — UPSC Content · Anantam IAS

Pooja Bhatt is part of the editorial team at Anantam IAS, writing and editing UPSC prep content across Prelims, Mains and current affairs.

Specialises in · UPSC syllabus content, editing and publishing Experience · 6+ years

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