India’s Semiconductor Mission has approved five fabs and committed ₹76,000 crore in incentives. Examine the strategic logic, the demand-supply gap, and the policy risks of building chip sovereignty.
Subtopic: Sci-Tech · Semiconductors
How to structure your answer
Introduction: India Semiconductor Mission (ISM) launched 2021 with ₹76,000 crore outlay; approved fabs include Tata-PSMC Dholera, Micron ATMP Sanand, CG Power-Renesas, Kaynes Sanand and Tata Jagiroad OSAT (cumulative ~₹1.5 lakh crore investment).
Body: 1) Strategic logic — chip imports ~$30 bn FY24; geopolitical concentration in Taiwan and Korea; Pax Silica framing. 2) Programme architecture — SPECS, DLI, modified incentive scheme covering 50% capex. 3) Risks — IP and talent gap, water and power needs (Dholera 110 ML/day), trailing-edge node focus (28-65 nm).
Way forward: Scale Semicon India 2.0 with leading-edge node pathway; expand C-DAC and IITs through Chips to Startup; align with US CHIPS Act dialogue and Quad supply chain.
Written within the word limit
219 words · target 250 words · 14 min
Introduction:
The India Semiconductor Mission, launched under MeitY in December 2021 with a corpus of ₹76,000 crore, has approved five fabrication and ATMP units — Tata-PSMC Dholera (28 nm logic), Micron Sanand, Tata-OSAT Morigaon, CG Power Sanand and Kaynes Sanand — committing investment of ₹1.5 lakh crore (PIB, March 2026).
Strategic logic: Global chip supply was disrupted by COVID-19 and the 2022 Taiwan contingency planning; the US CHIPS and Science Act 2022 ($52 bn) and EU Chips Act ($46 bn) reset state-backed industrial policy. India's mission aligns with QUAD Critical and Emerging Tech Working Group commitments and reduces import reliance — current chip imports were $28 bn in FY25 (DGFT data).
Demand-supply gap: Domestic semiconductor consumption will rise from $38 bn (2023) to $109 bn by 2030 (IESA-Counterpoint 2024). The five approved units cover only mature nodes (28 nm and above); leading-edge logic (sub-7 nm) remains absent, and the Compound Semiconductor Mission and the second tranche of ISM Phase-2 are awaiting Cabinet clearance.
Policy gaps: India lacks fab-grade ultra-pure water (8 million litres/day per fab), continuous power, ASML EUV access, and a deep talent pool — only 35,000 chip design engineers against a 2030 need of 1 lakh (NASSCOM 2024). The DLI scheme for design start-ups has approved 24 firms.
Way forward:
MeitY should clear ISM Phase-2 (₹40,000 crore additional) by FY27, integrate the Compound Semiconductor Mission, finance 85,000 Chips-to-Startup engineers under C2S, and align ISM with Skill India and IndiaAI Mission for sovereign capability.
What an examiner expects to see
- ISM outlay ₹76,000 crore (2021)
- Approved fabs — Tata-PSMC Dholera 28nm, Micron ATMP Sanand, Tata OSAT Jagiroad, CG-Renesas, Kaynes
- DLI scheme for fabless design
- MeitY and SemiconIndia programme
- Pax Silica — chip geopolitics framing
- Quad Critical and Emerging Technology Working Group
- Chips to Startup Programme — 85,000 engineers target
- Electronics Component Manufacturing Scheme (ECMS) 2025
Concrete cases, schemes and judgments
- Tata-PSMC Dholera fab (28-110nm)
- Micron Sanand OSAT first chip 2025
- Tata Jagiroad OSAT Assam
- L&T Semiconductor Technologies