The India Semiconductor Mission has committed ₹76,000 crore in incentives but the country still has only one mature-node fab approved. Discuss the structural composition of ISM 1.0 versus ISM 2.0 and the binding constraints below the fab gate.

Introduction:

The India Semiconductor Mission (ISM 1.0) was approved in December 2021 with a ₹76,000 crore outlay; by December 2025, MeitY had cleared 10 projects with ~₹1.6 lakh crore committed across six states. The Tata-PSMC fab at Dholera remains the only approved front-end fab, exposing the depth of the ecosystem gap below the fab gate.

ISM 1.0 composition:

The portfolio comprises one fab — Tata-PSMC Dholera, up to ₹91,000 crore for 50,000 wafers/month at 28nm and above — plus five OSAT/ATMP units: Micron Sanand (₹22,500+ crore, inaugurated 28 February 2026), Tata Jagiroad in Assam (₹27,000 crore), CG Power-Renesas, Kaynes Sanand, and HCL-Foxconn. The Design Linked Incentive targets 100 design firms; ISRO's Vikram 3201 (2025) is the first indigenous 32-bit microprocessor.

Binding constraints below the fab gate:

Photoresist, slurry, specialty gases, ultra-pure water systems, and lithography equipment are imported. Semiconductor materials and equipment supply remains concentrated in US, Japan, Netherlands, and Taiwan. Sovereignty at the fab gate is therefore illusory without an indigenous materials and equipment ecosystem; the collapsed Vedanta-Foxconn JV (2023) underlined execution risk.

ISM 2.0 pivot:

ISM 2.0 (Budget 2026-27, ₹1,000 crore FY26 provision) shifts the lens to equipment, materials, design IP, and skilling — the missing 60% of the value chain.

Way forward / Conclusion:

Scale ISM 2.0 funding to match the ecosystem gap, deepen DLI past ₹1,500 crore revenue support for 20 design firms, secure critical minerals via KABIL and the Quad Semiconductor Supply Chain Initiative, and target 5% global wafer share by 2030 under MeitY.