The India Semiconductor Mission has approved five fabs and packaging units with Rs 76,000 crore in incentives. Examine the strategic logic and the limits of India’s chip strategy.
Subtopic: IR · Geoeconomics — semiconductors
How to structure your answer
Introduction: The India Semiconductor Mission (December 2021) anchors Programme for Development of Semiconductors and Display Manufacturing Ecosystem in India with Rs 76,000 crore outlay, expanded under ISM 2.0 in 2024.
Body: Three dimensions — (i) Approved units: Tata Electronics-PSMC fab in Dholera ($11 billion, 28 nm), Tata OSAT in Jagiroad, Micron OSAT in Sanand ($2.75 billion), Kaynes ATMP, CG Power-Renesas ATMP; (ii) Strategic logic: friend-shoring under US CHIPS Act 2022 dynamics, JIST trilateral with US and Japan, Quad Semiconductor Supply Chain Initiative; (iii) Limits: most approvals are packaging-assembly-test (OSAT) rather than leading-edge fabrication; talent gap of 250,000-300,000 engineers per the India Electronics and Semiconductor Association; capital-intensive long gestation.
Way forward / Conclusion: Move from 28 nm to 14 nm via Tata-PSMC roadmap, scale design-linked incentives for fabless start-ups under DLI scheme, and use iCET technology agreement for advanced lithography access.
Written within the word limit
141 words · target 150 words · 9 min
Introduction: The India Semiconductor Mission (December 2021) anchors the Programme for Development of Semiconductors and Display Manufacturing Ecosystem with Rs 76,000 crore outlay, expanded under ISM 2.0 in 2024.
Body: Three dimensions evaluate the strategy. First, approved units — the Tata Electronics-PSMC fab in Dholera ($11 billion, 28 nm), Tata OSAT in Jagiroad, Micron OSAT in Sanand ($2.75 billion), Kaynes ATMP and CG Power-Renesas ATMP cover the assembly-packaging value chain. Second, strategic logic — friend-shoring under the US CHIPS Act 2022, the JIST trilateral with the US and Japan, the Quad Semiconductor Supply Chain Initiative and iCET's lithography pathway frame India's pull-in. Third, limits — most approvals are OSAT, not leading-edge fabrication; the India Electronics and Semiconductor Association records a talent gap of 2.5-3 lakh engineers; capital intensity persists.
Conclusion: Move from 28 nm to 14 nm via the Tata-PSMC roadmap, scale Design-Linked Incentives for fabless start-ups and use iCET for advanced lithography access.
What an examiner expects to see
- India Semiconductor Mission — December 2021; Rs 76,000 crore (PLI + DLI)
- Tata Electronics-PSMC fab Dholera — $11 billion, 28 nm
- Micron OSAT Sanand — $2.75 billion (June 2023 approval)
- Tata OSAT Jagiroad (Assam)
- CG Power-Renesas-Stars Microelectronics ATMP
- Design-Linked Incentive (DLI) scheme for fabless start-ups
- Mostly OSAT/ATMP — not yet leading-edge fabrication
- Quad Semiconductor Supply Chain Initiative; JIST (US-Japan-India) trilateral
Concrete cases, schemes and judgments
- India Semiconductor Mission (December 2021)
- Tata-PSMC Dholera fab
- Micron Sanand OSAT
- Tata Jagiroad OSAT
- Design-Linked Incentive (DLI) scheme
- Quad Semiconductor Supply Chain Initiative